Using the VHDL-AMS Model Editor

The VHDL-AMS Model Editor automates the writing, editing, and compiling of VHDL-AMS entity declarations and architecture descriptions, generating much of the code required to implement VHDL-AMS models in Twin Builder. The VHDL-AMS Model Editor provides a text editor for editing and compiling the VHDL-AMS model code. The model editor manages syntax checking and component generation. You can also print the file listing.

Models generated using the VHDL-AMS Model Editor appear under Project Components in the Project Manager components tree, and are used in the same way as other Twin Builder components. Edit their properties with the Component Editor.

Related Topics 

• Text Editor Options
• VHDL-AMS Models in Twin Builder
• Adding a VHDL-AMS Model
• Editing a VHDL-AMS Model
• Saving Uncompiled Model Changes
• Checking Syntax
• Printing
• Instantiating a Predefined Component in an Architecture Description
• Updating a Project to Add a VHDL-AMS Model and Component
• Encrypting a VHDL-AMS Model
• Using IEEE Standard Encryption for VHDL-AMS Models in Twin Builder
• Revising an Existing VHDL-AMS Model with the VHDL-AMS Model Editor
• VHDL-AMS Model Editor Menus and Windows