VHDL-AMS Models in Twin Builder

VHDL-AMS (Very high-speed integrated circuit Hardware Description Language – Analog Mixed Signal) is a standardized language used for describing digital, analog, and mixed-signal systems.

The Institute of Electrical and Electronics Engineers (IEEE) standardized the VHDL-1076 language as a Hardware Description Language (HDL) for digital models. The VHDL standard from 1993 was extended in 1999 for the description of analog and mixed-signal models in the form of the IEEE 1076.1 standard for VHDL-AMS (hereafter referred to as VHDL).

See VHDL-AMS Language Fundamentals for detailed information on the VHDL-AMS language in Twin Builder.

You can access the VHDL-AMS Tutorial documentation within the help system.

In addition to the functionality provided by the VHDL-AMS Model Editor, Twin Builder supports the development and simulation of VHDL-AMS analog, digital, and mixed-signal models in the following ways:

• Import existing VHDL-AMS models in ASCII text into a library or a subsheet on a schematic.
• Export VHDL-AMS models in libraries, as well as text or graphical subsheets, to ASCII text files.
• Export schematics containing VHDL-AMS models as netlists to VHDL ASCII files.
• VHDL-AMS models can instantiate Twin Builder models as foreign models, so you can take advantage of the large number and variety of highly optimized and fast Twin Builder models.