Instantiating a Predefined Component in an Architecture Description

Structural VHDL-AMS architecture descriptions require the use of predefined component models. To instantiate a predefined component with the VHDL Model Editor:

1. Click VHDL Model Editor > Instantiate Component. The Instantiate Component dialog box opens.

2. Select the name of the Architecture description in which the component is to be instantiated.
3. In the Available Components section of the dialog box, browse to the desired component.
4. Double-click the desired component. A new instance of the model appears in the Instantiated Components section.

1. Type a name for the model instance in the Name field.
2. Select an entity and an architecture for the model instance from the lists available in the Entity and Architecture fields.

5. In the Ports section, enter a numerical value or the name of a port or generic in the Value field for each of the model instance's ports. Terminals should be mapped to other terminals, while quantities and signals can be mapped to ports of the same type, or to generics, or can just be given numerical values.
6. In the Generics section, select a value for each generic of the model. The value may be a numerical value or generic and can be typed into the field or selected from the list of available values in the Value field.
7. Once all desired model instances have been added to the architecture description, click OK. The editor generates the VHDL-AMS statements that instantiate the models and map their ports.