CPA Simulations

Chip-Package-Analysis (CPA) is a 3D Finite Element Method (FEM)-based tool for fast and accurate extraction of power and signal distribution networks on IC packages. It can generate per-bump resolution models (thousands of bumps) or user-defined pin grouped models, while preserving ground bounce. The model consists of a passive RLCG Spice netlist and includes package-mounted decaps.

A CPA model comprises DC resistance and low frequency inductance and capacitance effects. High resolution resistance and inductance color maps generated after running a CPA simulation help in package probing. A comprehensive HTML reporting feature summarizes the layout geometry, setup and simulation results. The CPA model can be seamlessly imported into Ansys RedHawk for Chip + Package cosimulation.

This section covers:

• CPA RLGC Simulation Setup
• Computing CPA RLGC Simulations
• Viewing CPA RLGC Results
• Exporting CPA RLGC Results
• Reduce Matrix Operations