VHDL-AMS Language Fundamentals
The VHDL-AMS language fundamentals described in this section provide a quick reference guide to find a specific statement, or the syntax for a specific statement, needed to write VHDL-AMS code.
For more information, visit the IEEE 1076.1 Working
Group at
http://www.eda.org/vhdl-ams.
The VHDL-AMS language is case insensitive; upper case letters are equivalent to lower case letters. In this document, reserved words are in UPPER case and shown in BOLD.
Identifiers are simple names starting with a letter and may have letters and digits. The underscore character is allowed but not as the first or last character of an identifier.
A comment starts with two consecutive hyphens, “--”, and continues until the end of the line.
The following table shows the syntax used in the documentation.
|
Syntax |
Description |
|
ENTITY |
VHDL-AMS keyword |
|
[expression] |
optional entry |
|
[name | string] |
alternative selection |
|
identifier{,…} |
repeated entries |
|
=> <= := |
assignment operators |
|
== |
simultaneous statement |