DDR Variables

Electronics Desktop contains variables which can be customized to facilitate quick adjustments and re-run of Analysis directly within Electronics Desktop. To adjust variable values, right-click the schematic project in the Project Manager and select Project Variables.

The table below lists DDR variables. For more general information on using variables in Electronics Desktop, consult the Circuit help.

Variable Description
$cornervals A fixed enumeration array with values "typ" (typical), "min" (minimum), "max" (maximum), "fast", and "slow".
$corner

An index on the $cornervals array, where 0 = "typ", 1 = "min", 2 = "max", 3 = "fast", and 4 = "slow".

If there is no common corner needed for all the IBIS models in the design, $corner is replaced with five variables:

  • $corner0 – will have a value of 0 and be used by all IBIS models that need corner value "typ".
  • $corner1 – will have a value of 1 and be used by all IBIS models that need corner value "min".
  • $corner2 – will have a value of 2 and be used by all IBIS models that need corner value "max".
  • $corner3 – will have a value of 3 and be used by all IBIS models that need corner value "fast".
  • $corner4 – will have a value of 4 and be used by all IBIS models that need corner value "slow".

For example, you needed to force the corner for all IBIS models to "max", you would change the value of all five of these variables to 2.
$voltage The VDD value. VTT will use $voltage/2.0.
$bitrate DDR speed.
$odt The On-Die Termination (ODT) value, in ohms.
$cterm The receiver side termination capacitance value.
$driverRPullUp The pull-up resistance value used in driver side Pseudo-Open Drains (PODs) for DDR4 and above.
$driverRPullDown The pull-down resistance value used in driver side PODs for DDR4 and above.
$outputImpedanceDQDQS Internal impedance on the driver side eye source for DQ and DQS nets.
$outputimpedanceADDRCLKOTHER Internal impedance on the driver side eye source for ADDR, CLK, and OTHER nets.
$addrNetRes Resistance termination value on the receiver side for ADDR nets.
$clkNetRes1 Positive net resistance termination value on the receiver side for CLK nets.
$clkNetRes2 Negative net resistance termination value on the receiver side for CLK nets.
$clkNetCap Capacitance termination value on the receiver side for CLK nets.
$clkNetCapDiff Differential Capacitance termination value on the receiver side for CLK nets.
$<netName>_delay

Delay applied based on strobe/clock assignments.

For example:

  • $DIFF_DQS0_delay is applied to nets DQ0 through DQ7 and also to net DIFF_DQS0.
  • $DIFF_DQS1_delay is applied to nets DQ8 through DQ15 and also to net DIFF_DQS1.
  • $CK0_delay is applied to nets AD0 through AD15 and also to net CK0.
$DQ_nets_delay Delay applied to every net in the DQ group. Default is 0 for both DDR modes.
$DQS_nets_delay Delay applied to every net in the DQS group. Default is 0 for DDR Read Mode and half the bit width of the DQ net for DDR Write Mode.
$CLK_nets_delay Delay applied to every net in the CLK group. Default is 0 for DDR Read Mode and one bit width of the ADDR net for DDR Write Mode.
$ADDR_nets_delay Delay applied to every net in the ADDR group. Default is 0 for both DDR modes.
$OTHER_nets_delay Delay applied to every net in the OTHER group. Default is 0 for both DDR modes.
$steprespnumui

Determines how long an AMI analysis runs and is used by all IBIS AMI sources. It can be determined by analyzing the impulse response of the AMI solve to see how many unit Intervals it takes to completely settle.

For DDR simulations, the ideal values are used as default:

  • Value of 10 if DDR speed is within 3200Mbps
  • Value of 15 if DDR speed is between 3200Mbps and 4800Mbps
  • Value of 20 if DDR speed is above 4800Mbps.

Change to a appropriate value, if appropriate.
Related Topics:

Cosimulation using DDR Wizard

Running Simulations in DDR Wizard

DDR Wizard Settings