Creating Twin Models

Follow these steps to create a Twin model using the schematic editor.

Note:

An example of this procedure is located in "...\ANSYS Inc\v252\AnsysEM\Examples\Twin Builder\Applications\Twin Generation\CoupledClutches.aedt".

Note:

Only subcircuits that contain one or more of the following components can be compiled into a Twin model:

  • FMU
  • Modelica
  • UnitDelay (located in the Simplorer Elements\Basic Elements VHDLAMS\Blocks\Discrete Blocks library)
  1. Open a Twin Builder design.
  2. Open the top level design in the schematic editor.
  3. Select the desired subcircuit design instance on the schematic that you want to compile as a Twin component.
    4. Note:

    When compiling a Twin, you must break any algebraic loop formed when a feedback loop exists between components on the subsheet.

    The UnitDelay component holds and delays its input by a sample time parameter (ts) that you specify.

    Follow these steps to add a unit delay component to a feedback loop.

    1. Open a Twin Builder design.

    2. Go to the Component Library and find the udelay component (the Unit Delay Model in VHDL-AMS under Simplorer Elements\Basic Elements\VHDLAMS\Blocks\Discrete Blocks).

    3. Select the udelay library and create an instance on the subsheet where a feedback loop exists.

    4. Connect the pins of the udelay instance to the pins of the feedback loop.

    5. Set the sample time parameter (ts) according to your transient analysis; for example, a ts equal to the time step at which your twin is being simulated.

  4. Right-click the selected subcircuit instance and select Compile As Twin Model. The Compile Twin Model dialog box appears.
  5. In the Compile Twin Model dialog box, you can change the Twin model name and various model-dependent options (solver method, step size, relative and absolute tolerance).
    6. Note:

    If compiling an FMU, the full path and file name must not exceed 256 characters or the compilation will fail. If the Twin model does not generate, check your local TEMP folder to see if the dtrg_error_*.log file generated. This log can help identify and explain common errors in Twin compilation.

  6. Click Compile to compile the subcircuit as a Twin model. which you then add to the project under Project definitions > Components. It will be also added to mouse cursor ready to be placed anywhere on the schematic.

Recompiling and Update Existing Twin Component

In the Compile Twin Model dialog box, use the previously created Twin model name to update the existing Twin component.

Related Topics 

Exporting a Twin Model as a Twin