Names of Components and Variables
User-defined names can be given to components, blocks, states, time functions, characteristics, nodes, ports, and standard variables. Names may contain any combination of uppercase and lowercase letters (A-Z, a-z), the numerals 0 through 9, and underscores – and can have a maximum of 50 characters.
Note:
- In general, user-defined names are case-sensitive. However, names of components and variables of VHDL-AMS models are case-insensitive and all uppercase letters are converted to lowercase.
- Do not duplicate names (for example, R1 and r1). Duplicate instance names result in netlist errors when attempting to compile a circuit prior to analysis.
- The first character of a name must always be a letter.
- Vowel mutations (for example, umlauts) are not allowed.
- Spaces are not allowed.
The following predefined variable types are not allowed for names:
- SML notation keywords.
- Simulation parameters.
- System variables.