About the VHDL-AMS working Library in Twin Builder
According to the VHDL-AMS language definition, all design units (for example, models or packages in Twin Builder) are compiled into the working library (work) from which all following analysis steps take the model for further processing. Generally, VHDL-AMS tools keep only the latest compiled version of a design unit in this working library. The origin of the design unit is lost in this process. That also means that in order to guarantee the correct creation of a structural design, all design units must be compiled at the same time, and the order of compilation must be according to the units’ dependencies.
Twin Builder follows an approach that allows for greater control over these references. Although win Builde has a similar working library (project), this library can contain multiple design units that have the same definition name but were loaded from different libraries. The interfaces and contents of these models (or packages, but we'll refer to just models below for simplicity) do not have to match each other. For this reason, all models in the project library preserve their original library locations; and in order to access a specific model, the original library location must be specified together with the model name. In addition, project itself is a regular library that is used as the origin for models that were imported from text files or created manually using the VHDL-AMS Model Editor.
In other VHDL-AMS systems, if a model def refers to a model using work.abc, def will access the current model abc in the working library. When using def, however, the abc in the work library to which work.abc refers may not be the same abc that was used in the creation and testing of def.
References to work.abc are handled with more specificity in Twin Builder. The library that abc came from is kept with abc and when, as above, a model def references work.abc, then the same abc will be used for def as was used in its creation and testing.
Even though Twin Builder can define a library alias name work (this would load models specified by work.abc from the aliased library), it does not have the same behavior as in other VHDL tools. The library concept used in Ansys Electromagnetics tools does not allow automatic writing to any library other than project. You can only write to another library by manual export.