Trace Mapping Using a Layout Component

Trace mapping is a means of representing printed circuit boards (PCBs) in a simulation model. The electrically conductive, and structurally stiffer, traces of a PCB (including pads, vias, and conductor pour areas) are accounted for without actually including the conductor geometry in the Icepak design. Use a previously created HFSS 3D Layout design as a source for Adding a Layout Component to your Icepak design. The conducting objects are visualized in the layout component, but they are not directly included as 3D geometry.

The signal layers exists in the Icepak design as a contiguous volume of the layer's dielectric fill material. The solver modifies the fill material's properties locally, element-by-element, based on a metal fraction map, which is derived from the source layout's conductor geometry. The resolution of the metal fraction map is user-defined and needs to be fine enough to accurately capture the metal distribution on the board's signal layers. Metal fraction values are also mapped along the full length of vias, through dielectric and signal layers.

Significance of the metal fraction map resolution: You define the number of columns and rows into which the board's length (X dimension) and width or height (Y-dimension) are to be divided. You can specify the resolution numerically or using a slider. Each cell in the resulting grid is assigned a value between 0 and 1, inclusively. The numbers represent the decimal portion of each cell that consists of conducting metal. For example, a value of 0.45 indicates that 45 percent of the cell is metal and therefore, 55 percent is dielectric. The thermal material properties of all elements will be somewhere between the dielectric/fill material and the conductor material, inclusively. When an element extends into two or more grid cells, the element's metal fraction value is interpolated, and the material properties are based on the interpolated metal fraction value.

PCB Grid Resolution

The grid resolution that is used to create the thermal conductivity distribution of the board can be customized. Depending on the trace resolution and the computational costs desired, you can change the values for the columns and rows to receive optimum results. The size of the grid is in parentheses next to the column and row count.

The following points outline best practices for balancing accuracy and cost of computing the cell by cell orthotropic thermal conductivity:

• For board-level simulations, enter column and row counts that yield at most a grid size equal to the minimum trace width or minimum via diameter. If possible, use column and row counts that yield a grid size equal to half the minimum trace width or half the minimum via diameter.

• For system-level simulations, enter column and row counts to yield at most a grid size that equals four to eight times the minimum trace width or minimum via diameter.

• For all models, the CFD mesh on the board should equal four to eight times the grid size.

• Column and row counts or CFD meshes that significantly deviate from the above guidelines can adversely affect accuracy.