A number of use cases/features have been identified in the pre-assessment stage by ANSYS experts as potentially having a critical impact on decisions during system design analysis. These parts of the tool fall into the scope of tool qualification:
Feature Set "Failure rate computation":
[FR1.1] Computation of failure rates based on SN 29500
[FR1.2] Computation of failure rates based on IEC 62380
[FR1.3] Computation of failure rates based on FIDES Guide (2009)
[FR1.4] Computation of failure rates based on MIL Handbook 217, Notice F
[FR1.5] Distribution of failure rates over failure modes
[FR1.6] Inheritance of failure modes failure and distribution via type library
[FR1.7] Propagation of failure via failure net cause relation
[FR1.8] Computation of failure rates based on Handbook 217PlusTM
[FR1.9] Computation of failure rates based on IEC 61709
[FR1.10] Computation of failure rates based on GJB/Z 299C
[FR1.11] Take-over of failure rates from databases (NPRD, EPRD)
Feature Set "Fault Tree Analysis (FTA)":
[FTA1.1] Quantitative calculation using basic probability models (fixed, exponential, repairable, monitored, risk time model, Weibull)
[FTA1.2] Quantitative calculations of gates (AND, OR, XOR, NOT, Voting, Transfer)
[FTA1.3] Target values for unavailability, unreliability, CFI, and MTTF/MTBF based on mission time parameters
[FTA1.4] Derivation of probabilities from failure rates of SysML elements
[FTA1.5] Calculation of minimal cut sets
Feature Set "Failure Mode Effect and Criticality Analysis (FMECA)":
[FMECA1.1] Computation of failure mode criticality numbers
[FMECA1.2] Computation of component citicality numbers
Feature Set "Failure Mode Effect and Diagnostic Analysis (FMEDA) and Single Point/Latent Fault Metric evaluation":
[DC1.1] Single Points Fault Metric for multiple safety goals (ISO 26262)
[DC1.2] Latent Point Fault Metric for multiple safety goals (ISO 26262)
[DC1.3] Safe Failure Fraction and Diagnostic Coverage for FMEDA (IEC 61508)
[DC1.4] Variant support for all FMEDA metrics (SPF/LF/SFF/DC)
Feature Set "IP Design Processing" for semiconductors:
[IP1.1] Import and Update of IP Design data
[IP1.2] Aggregation of chip data into a higher-level SysML model based on allocations
Feature Set "Reliability Block Diagrams (RBD)":
[RBD1.1] Quantitative calculation using basic probability models at blocks (fixed, exponential, repairable, monitored, risk time model, Weibull)
[RBD1.2] Quantitative calculations of R(t) with series and parallel configurations, nesting of blocks, and transfer gates to FTA
[RBD1.3] Target values for unavailability, unreliability, CFI, and MTTF/MTBF based on mission time parameters
[RBD1.4] Calculation of minimal cut sets
For this set of critical tool features the provided qualification tests ensure that the listed features will behave in the same way as specified and tested at ANSYS Germany GmbH.
Note that further capabilities are by default not covered by the Tool Qualification Kit and need to be assessed for critical impact on a case by case basis. Especially further customization and automation through profile properties and scripts must be assessed (and potentially qualified) in addition to this toolkit.