A component declaration defines a component’s interface and is typically placed in an ARCHITECTURE or PACKAGE declaration. The component or instances of the component are related to a design entity in a library using a configuration.

COMPONENT component_name [IS]

[local_generic_clause]

[local_port_clause]

END COMPONENT [component_name];

component_name

Name of the component.

local_generic_clause

Specifies static information to be communicated to a model from its environment in this form: variable_name: variable_type := value;

local_port_clause

Specifies dynamic information communicated to a model from its environment in this form: variable_name: port_mode variable_type;

ENTITY inv4 IS

GENERIC (TP_LH, TP_HL: TIME);

PORT (I_4 : IN BIT_VECTOR(3 DOWNTO 0);

Y_4 : OUT BIT_VECTOR(3 DOWNTO 0));

END ENTITY inv4;

ARCHITECTURE inv4_struct OF inv4 IS

COMPONENT inv

GENERIC (TP_LH, TP_HL: TIME);

PORT (I1 : IN BIT;

Y1 : OUT BIT);

END COMPONENT;

SIGNAL INV_OUT : BIT_VECTOR(3 DOWNTO 0);

BEGIN

-- instantiation of the inv component

INV_1 : inv GENERIC MAP (TP_LH,TP_HL) PORT MAP (I_4(0),Y_4(0));

INV_2 : inv GENERIC MAP (TP_LH,TP_HL) PORT MAP (I_4(1),Y_4(1));

INV_3 : inv GENERIC MAP (TP_LH,TP_HL) PORT MAP (I_4(2),Y_4(2));

INV_4 : inv GENERIC MAP (TP_LH,TP_HL) PORT MAP (I_4(3),Y_4(3));

END inv4_struct;