Computing DC IR Simulations in HFSS 3D Layout

DC IR analysis solves for the voltage drop across the power plane. The DC solution provides important information pertaining to power delivery, including:

• Status of the voltage regulator to determine if it is functioning and supplying the proper DC voltage to all active components attached to power rails
• DC current density information to warn where board or via damage may occur

HFSS 3D Layout makes use of the Ansys SIwave™ DC solver that is based on a well-known formulation and produces an efficient DC solution.

HFSS 3D Layout can perform the following actions:

• Add current sources, voltage sources, voltage probes, and DC terminals
Note:

DC terminals are not currently supported within the IC Mode environment. The terminal icon will not appear in either the menu or ribbon.

• (General Mode Only) View and create Voltage Regulators (VRMs)
• (General Mode Only) Define equipotential regions
• Compute DC current and voltage distribution
• Export DC IR simulation results
• (General Mode Only) Export DC IR data to Icepak, or import a temperature map from Icepak to use in the DC IR simulation
• Plot DC IR field overlays
• (General Mode Only) Overlay a DC Temperature Field

From General mode, users can configure component parameters prior to simulation from the SIwave Workflow Wizard or skip directly to Setting Up the Compute DC Current and Voltage Distribution Window.

Computing DC IR Simulations in IC Mode

Users can create DC IR analysis solves in both General mode and IC mode. IC Mode integrates ECAD Xplorer into the HFSS 3D Layout environment, preserving ECAD Xplorer's capabilities of creating larger, more complex IC models, while allowing users direct access to most General Mode features (Refer to Layout Editor), with some notable differences:

• The SIwave Workflow Wizard is not available in IC Mode. IC Mode users can skip directly to Setting Up the Compute DC Current and Voltage Distribution Window.
• Voltage sources, current sources, and voltage probes are supported. DC terminals are not currently supported.
• The Compute DC Current and Voltage Distribution window contains a subset of options available in General mode. Options unique to General mode are noted in the instructions.
• All simulation results are available to view and export, except the DC Power Tree.
• Overlapping stackups are supported. In General Mode, only laminate stackups are supported.

Beginning Simulation From the SIwave Workflow Wizard (General Mode Only)

Follow these steps to begin configuring a simulation from the SIwave Workflow Wizard.

1. From the Layout tab, select Worfklow to open the SIwave Workflow Wizard window.



2. Click Configure DC IR Drop Analysis to open the DC IR Configuration window.



3. From the list on the left, check the box adjacent to a selected net (e.g., BST_V1P0_S0).



4. From the table, do the following:
1. Make selections from the Source/Probe drop-down menu (i.e, select from None, Current Source, Voltage Source, Voltage Probe, or Terminal).
2. The Type drop-down menu is enabled if Current Source or Voltage Probe are selected from the Source/Probe drop-down menu. Select either Constant Voltage (i.e., adding one circuit element) or Distributed Current (i.e., adding a circuit element on every pin) from the Type drop-down menu.



3. Enter a Magnitude in the adjacent field or accept the default parameter, if any.
4. Select the left-most empty cell in the component's row to populate the fields beneath the table. Then make further adjustments, as appropriate.



5. Click Configure Simulation.



6. Click Validate to open the Launch Geometry Check window.



7. If applicable, configure the validation check. Then click OK to begin validation. View progress in the Progress window.



Note:

Users will need to open the Progress window and position it conveniently beforehand.

8. After the validation check is complete, a Geometry Check Results window appears. Assuming the simulation has passed validation, click OK to return to the DC IR Configuration window.



9. Click Simulate to open the Compute DC Current and Voltage Distribution window.



10. Continue to step 2 of Computing DC IR Simulations in HFSS 3D Layout .

Setting Up the Compute DC Current and Voltage Distribution Window

Follow these steps to finalize simulation solver setup and run a simulation computing DC current and voltage distribution.

1. From the Project Manager window, expand the Project Tree and Active Design Folder. Then right-click Analysis.



2. Do one of the following to open the Compute DC Current and Voltage Distribution window.
• From General mode, select Add SIwave Solution Setup > Add SIwave DCIR Solution Setup.



• From IC Mode, select Add DCIR Solution Setup.



Then select Add SIwave DCIR Solution Setup to open the Compute DC Current and Voltage Distribution window.



3. From the Compute DC Current and Voltage Distribution window, do the following:



• Simulation name – enter a name for the DC IR simulation.
• (General Mode Only) From the Excitations area, select a source of excitations (i.e., Use sources defined in the project or Use sources defined in external file). If the user selects Use source defined in external file, Browse to an appropriate file and select it (e.g., test.tmp).
• (General Mode Only) From the Ansys Icepak Options area, there are two optional settings:
• Check Export power dissipation for use in Ansys Icepak^® and Mechanical to export data to either of these design types.
• Check Import temperature map to select an Ansys Icepak/Ansys SIwave temperature distribution file, then Browse to an appropriate file and select it (*test.sitemp). The temperature data can locally adjust DC conductivity.
• From the Select Ideal Ground Node(s) area, select a ground node on the table. Select a current or voltage source at 0 volts (ideal ground). All other voltages are computed with respect to this node. If no ideal ground node is selected, HFSS 3D Layout automatically picks a source terminal to ground.

Click the Node to Ground drop-down menu to select Neither, Negative, or Positive.

If a Negative voltage source is selected, the voltage display on its ground pin is 0 V.

If a Positive voltage source is selected, the voltage display on its ground pin are negative.

Note:

Assume that the selection is the 0 node in a SPICE simulation. This is the node to which all voltages should be referenced. Since HFSS 3D Layout includes the return paths of all planes (including ground), do not assume all the sources reference that 0 node. An absolute 0 node reference must be selected. So if the 0 node is on the positive side of a voltage plane, the "ground" or return path is shown as negative.

4. To view additional solver options, click Other solver options. The SIwave Solution Setup window opens, on the DC tab.



From this window, do the following:

• Use the slider to balance speed and accuracy:
• Optimum Speed – all options in the DC Advanced tab are deactivated.
• Balanced – the Mesh Bondwires and Mesh Vias options are selected, along with adaptive Mesh Refinement.
• Optimum Accuracy – the mesh are refined on bondwire and vias, and more aggressive refinement parameters are specified.
• Select whether to Compute Inductance. The inductance is computed by integrating the vector potential at DC using an efficient, multi-level fast multipole method with two-level parallelization. In some cases, this may require significant computational time and memory.
• Select whether to use Custom simulation settings.
• Select whether to Plot Current Density and Voltage Distribution. Clear this check box to save disk space if users do not need to post-process voltage and current plots (e.g., if the user only want to export a SPICE netlist after a DC simulation, it might not be helpful to save any field data to disk).
• Enter the Circuit Element Contact Radius. Equal potential is enforced in the contact radius, and no mesh refinement is done inside the contact region.
5. Check Custom to enable DC Advanced settings, then select the DC Advanced tab.



DC Advanced options include:

• Ignore geometry smaller than – geometry whose area (after being combined with any overlapping geometry) falls under this specified threshold is ignored during simulation.
• Ignore voids smaller than – geometry whose area (after being combined with any overlapping geometry) falls under this specified threshold is ignored during simulation.
• Snap vertices separated by less than – entities (e.g., vias) and vertices that are separated by less than the distance specified in this box may be snapped together during solver pre-processing.
• Initial Mesh Max. Edge Length – specifies the maximum edge length selected in the mesh (before any adaptive refinement occurs).
• Mesh Bondwires – check if users do not want to model bondwires as point connections to mesh. Specify the Bondwire Discretization (the number of sides used to approximate cylindrical bondwires). Specify any value between 6 and 64. The default value is 8.
• Mesh Vias – check if users do not want to model vias as point connections to mesh. Specify the Via Discretization (the number of sides used to approximate cylindrical vias). Specify any value between 6 and 64. The default value is 8.
• Perform Adaptive Mesh Refinement – check to perform Adaptive Mesh Refinement, and populate the fields:
• Minimum Number of Passes – an adaptive analysis does not stop unless the minimum number of passes specified has been completed, even if convergence criteria have been met.
• Maximum Number of Passes – this value is the maximum number of mesh refinement cycles users want the simulation to perform. This value is a stopping criterion for the adaptive solution. If the maximum number of passes has been completed, the adaptive analysis stops; otherwise, the adaptive analysis continues unless the convergence criteria are reached.
Note:

The size of the finite element mesh — and the amount of memory required to generate a solution — increases with each adaptive refinement of the mesh. Setting the maximum number of passes too high can result in the Ansys Electronics Desktop (AEDT)^TM electronics systems design platform requesting more memory than is available or taking excessive time to compute solutions.

• Local Refinement – this value determines how many triangles are added at each iteration of the adaptive refinement process. The triangles with the highest error is refined. The default value is 20%.
• Energy Error – the default value is 2%.
• Refine Mesh Along Bondwires – check to refine mesh along bondwires.
• Refine Mesh Along Vias – check to refine mesh along vias.
6. Select the S-Parameters tab.

   

7. Select State Space Model or Custom Model. If Custom Model is selected, set the following options:
• Interpolation – select Point, Linear, or Step from the drop-down menu.
• Extrapolation – select Zero padding, Same as last point, Linear extrapolation from last 2 points, or Constant magnitude linear phase extrapolation from the drop-down menu.
• DC Behavior – select Zero padding, Same as last point, Linear extrapolation from last 2 points, or Constant magnitude linear phase extrapolation, Series Capacitor, or Leave all signal lines open circuited from the drop-down menu.
Note:

Refer to the following pages for an example of using the SIwave Solution Setup window to change S-Parameters or using a preconfigured Python script to generate an Ansys ECAD database file, which can then be imported into AEDT to create a custom Ansys SIwave setup.

8. After making any selected changes, click OK to exit the solution setup.
9. Click OK to save the solution setup. The Project Manager window updates to show the DC IR setup under Analysis.

   

10. (General Mode Only) Run through the SIwave Workflow Wizard.
11. From the Project Manager window, right-click the analysis and select Analyze.



12. The Progress window displays the simulation's progress. When it finishes, view or export results.