Design Units

The VHDL-AMS language allows the definition of models for analog, digital, and mixed signal circuits and systems in a standardized language. Design units (also library units) are segments of VHDL-AMS code that can be compiled separately and stored in a library.

An entity normally consists of five basic elements, or design units: entities, architectures, packages, package bodies, and configurations. Entities and architectures are the only two design units that must exist in any VHDL-AMS design description. Packages and configurations are optional.