VHDL-AMS Simulation

The VHDL-AMS simulator is a sub-simulator of the Twin Builder system. It calculates simulation models described in VHDL-AMS (Very high speed integrated circuit Hardware Description Language - Analog Mixed Signal). The SML compiler starts the VHDL-AMS simulator if VHDL-AMS models are used in the simulation model.

Components for VHDL-AMS Simulation

• Components in the Basic Elements VHDLAMS component library.
• Components in the Digital component library.
• Components implementation using VHDL-AMS.