Signal Assignments with Delay
VHDL-AMS offers several variants to perform signal assignments. The following example shows three delay forms:
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ENTITY sequential_sig_assign IS PORT(SIGNAL output: out bit); END; ARCHITECTURE behav OF sequential_sig_assign IS SIGNAL sig_s,sig_t,sig_i,sig_r : bit; BEGIN sig_s <= '1' AFTER 1 ms, '0' AFTER 5 ms, '1' AFTER 10 ms, '0' AFTER 13 ms, '1' AFTER 18 ms, '0' AFTER 20 ms, '1' AFTER 25 ms, '0' AFTER 26 ms; PROCESS (sig_s) BEGIN sig_t <= TRANSPORT sig_s AFTER 3 ms; -- signal assignment 1:1 sig_i <= INERTIAL sig_s AFTER 3 ms; -- signal assignment without signals smaller than delay time are supressed sig_r <= REJECT 2 ms INERTIAL sig_s AFTER 3 ms; -- signal assignment without signals smaller than reject time are suppressed END PROCESS; END; |
The following figure shows the results of the previous modeling code. The signal sig_s is delayed and assigned to signals in three different ways:
- The signal sig_t represents sig_s with a delay of 3ms.
- The signal sig_i represents sig_s with a delay of 3ms without signal changes occurring in an interval smaller than delay time.
- The signal sig_r
represents sig_s with a delay of 3ms
without signal changes occurring in an interval smaller than reject time.
