Design Verification (DV) employs layout-constraint rules which ensure the IC/PCB operates as designed, given the manufacturing process. Using DV, layers have restrictions on size, aspect ratio, and separation that result from different physical, chemical, and lithographic process limitations, and the electrical properties of the device.
DV rules to enforce these restrictions can be complex and involve layer and connectivity interactions. Before sending the IC/PCB layout to be manufactured, you should first verify the layout using the DV software:
- For IC, the manufacturing foundry specifies the restrictions. IC foundries require checking with an authorized DV rule set to guarantee the manufacturing.
- For PCB, companies that create the board design often have their own restrictions that also incorporate additional restrictions which come on the board manufacturer.
Vendors of DV software work with foundries to provide authorized sets of design rules to meet the process requirements.
Partial Rule Checking
It is common for the DV of a full layout to take hours to run. Since it is not practical to do such a check often, DV tools also provide partial design testing. Using a combination of complete and partial testing speeds up development time. Another time saver is using DV tools that can run directly on the layout editor database to avoid data translation.
DV is time-consuming and execution speed is a consideration. However, the top priority is accuracy. Both the foundry/manufacturer and company designing the IC/PCB rely on the accuracy of the results. False errors are better than missed errors, but they slow down the design cycle.
Graphical Data
The execution of a DV rule produces graphical data (polygon or edge/vector) showing location and explanatory error messages. The error messages may be output on the screen and/or included in the file of a generated report. One or more reports are created during a design verification run. The graphical data can be stored with the layout data or separately. Both the textual and graphical results can be used to locate and fix errors, but it is faster and more convenient to work with the graphical results accessed by a layout editor.
Hierarchical Checking
Hierarchical checking is used to speed up design verification.
Layouts that use hierarchy to partition segments of the layout enable DV programs to check identical segments only once and use the results for each placement. Note the advantage of hierarchy is greatly reduced if there is interaction with other objects at other levels of hierarchy.
Some DV tools analyze the actual layout hierarchy/geometry , then synthesize a hierarchical view that works best for design verification. Users can also modify portions of the layout hierarchy to “flatten” or ignore portions for checking. The verification view of the hierarchy does not change the actual hierarchy used in the layout.
Generated Results
Rule sets, runs, scripts, and generated results are all persistent, and are contained in the project file. Results are stored as solution data in the results file associated with the project file. Rule sets, runs, and scripts may be part of technology files to jump start new projects with existing DV checks.